1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating same, and more particularly, to a semiconductor device having conductive layers which are adjacent and parallel to one another and a contact plug which is formed between the conductive layers and a method for fabricating same.
2. Description of the Related Art
As semiconductor devices become highly integrated, there have been efforts to form many elements and wiring configurations in a limited area. In an example of such efforts, a capacitor is formed such that the capacitor is positioned over a bitline (COB) in a dynamic random access memory (DRAM) device. In the DRAM device, a metal-oxide seimconductor (MOS) transistor is formed on a substrate, and a capacitor is formed over a bitline, which outputs a data signal to a source. In addition, the capacitor is connected to a drain. Thus, such a capacitor structure needs a smaller area than when the capacitor is directly formed on the substrate.
In order to achieve such a capacitor structure, a plurality of contacts, e.g., a via contact or a contact plug, are required as a vertical conductive path which connects elements with other elements or elements with wires on different layers. Moreover, the contacts should be formed in a region so as to avoid bitlines serving as another conductive path. Thus, in order to form these contacts in a region other than the pre-existing conductive layer (e.g., bitline), the conductive layer is often coated with an insulating material having a different etching selectivity than the conductive layer and a self-aligned contact hole is formed by etching the insulating material. Here, the contact plug, which is formed by filling a conductive material in the self-aligned contact hole, will be referred to as a self aligned contact (SAC).
FIGS. 1 through 3 are vertical sectional views of bitlines showing a peripheral configuration of the bitlines in a conventional semiconductor device.
Referring to FIG. 1, two bitlines 20 are formed in parallel to each other. A storage node contact plug 60 is formed as an SAC between the bitlines 20 to electrically connect a contact pad or a drain region (not shown) under the bitlines 20 with a storage node (not shown) over the bitlines 20. A width of an entrance of the storage node contact plug 60 is larger than or equal to the distance between the bitlines 20. Capping layers 30 or spacers 40 are used to protect the bitlines 20 and if the capping layers 30 and spacers 40 are not formed, the bitlines 20 may be damaged during the formation of a contact hole H. Moreover, a short of the bitlines 20 and the conductive material that fills the contact hole H to form the storage node contact plug 60, may occur, thereby causing an abnormal function of the semiconductor device.
In an attempt to solve such a problem, a recent study used a capping layer 30 formed of silicon nitride and spacers 40 to surround the bitlines 20. Since interlayer insulating layers 10 and 50, in which the contact hole H is formed, are formed of silicon oxide, the interlayer insulating layers 10 and 50 have a different etching selectivity from the silicon nitride of the capping layer 30 when the interlayer insulating layers 10 and 50 are etched to form the contact hole H. Therefore, during formation of the contact hole H, most of the capping layer 30 and the spacers 40 exposed during the etching process remain while the interlayer insulating layers 10 and 50 between the spacers 40 are completely removed, and thus resulting in the formation of the contact hole H.
However, since a thick spacer 40 is used to prevent shorting of the bitlines 20 and the storage node contact plug 60, it is difficult to fill a space between the bitlines 20 with the interlayer insulating layer 50. That is, silicon oxide is deposited in a small space between the bitlines 20, but the space between the bitlines 20 is not fully filled with the silicon oxide. This results in the formation of a void inside the interlayer insulating layer 50 or a seam on the surface of the interlayer insulating layer 50. The void or the seam causes an error during a photo process or a contact hole H that is not fully open after the contact hole H's formation. In addition, since the spacer 40 is thick, an open area of the contact hole H becomes small, resulting in the contact hole H wherein it is difficult to reduce resistance.
FIG. 2 represents a case where two types of spacers 42 and 44 are applied. Under a strict design rule, a first spacer 42 would have to be very thin. Therefore, during the contact hole H formation, the first spacer 42 is recessed up to an upper portion of the bitlines 20 by etching the interlayer insulating layers 10 and 50. Accordingly, even when a second spacer 44 is formed in an innerwall of the contact hole H, the contact hole H is vulnerable to short-circuiting of the storage node contact plug 60 and the bitlines 20. If the second spacer 44 is thickened so as to prevent such shorting, the open area of the contact hole H becomes small, which makes it difficult to reduce a contact resistance.
Meanwhile, FIG. 3 shows a method of forming the contact hole H without forming spacers at the sidewalls of the bitlines 20 and forming a spacer 46 in the innerwall of the contact hole H. However, since there is no spacer which prevents the bitlines 20 from being etched during the contact hole H's formation, it is very difficult to prevent short-circuiting of the storage node contact plug 60 and the bitlines 20 if a misalignment of the contact hole H and the bitlines 20 occurs.